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cmos low cost, 10-bit multiplying dac ad7533 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features low cost 10-bit dac low cost ad7520 replacement linearity: ? lsb, 1 lsb, or 2 lsb low power dissipation full 4-quadrant multiplying dac cmos/ttl direct interface latch free (protection schottky not required) endpoint linearity applications digitally controlled attenuators programmable gain amplifiers function generation linear automatic gain controls general description the ad7533 is a low cost, 10-bit, 4-quadrant multiplying dac manufactured using an advanced thin-film-on-monolithic- cmos wafer fabrication process. pin and function equivalent to the ad7520 industry standard, the ad7533 is recommended as a lower cost alternative for old ad7520 sockets or new 10-bit dac designs. ad7533 application flexibility is demonstrated by its ability to interface to ttl or cmos, operate on 5 v to 15 v power, and provide proper binary scaling for reference inputs of either positive or negative polarity. functional block diagram 20k ? s1 s2 s3 sn i out 2 v ref i out 1 r fb 20k ? 20k ? 20k ? 10k ? bit 1 (msb) bit 10 (lsb) digital inputs (dtl/ttl/cmos compatible) bit 2 bit 3 10k ? 10k ? 10k ? 20k ? 01134-001 figure 1.
ad7533 rev. c | page 2 of 12 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 ter mi nolo g y ...................................................................................... 5 pin configurations and function descriptions ........................... 6 circuit description ............................................................................7 general circuit information ........................................................7 equivalent circuit analysis .........................................................7 operation ............................................................................................8 unipolar binary code ..................................................................8 bipolar (offset binary) code .......................................................8 applications ........................................................................................9 outline dimensions ....................................................................... 10 ordering guide .......................................................................... 12 revision history 3/07rev. b to rev. c changes to table 1............................................................................ 3 changes to table 2............................................................................ 4 changes to figure 13, figure 14, and figure 17 ........................... 9 updated outline dimensions ....................................................... 10 changes to ordering guide .......................................................... 12 1/06rev. a to rev. b updated format..................................................................universal changes to absolute maximum ratings ....................................... 4 added pin configurations and function descriptions section................................................ 6 updated outline dimensions ....................................................... 10 changes to ordering guide .......................................................... 12 3/04rev. 0 to rev. a changes to specifications.................................................................2 changes to absolute maximum ratings........................................3 changes to ordering guide .............................................................3 updated outline dimensions..........................................................7
ad7533 rev. c | page 3 of 12 specifications v dd = 15 v, v out 1 = v out 2 = 0 v, v ref = 10 v, unless otherwise noted. table 1. parameter t a = 25c t a = operating range test conditions static accuracy resolution 10 bits 10 bits relative accuracy 1 ad7533jn, ad7533aq, ad7533sq, ad7533jp 0.2% fsr maximum 0.2% fsr maximum ad7533kn, ad7533bq, ad7533kp, ad7533te 0.1% fsr maximum 0.1% fsr maximum ad7533ln, ad7533cq, ad7533uq 0.05% fsr maximum 0.05% fsr maximum dnl 1 lsb maximum 1 lsb maximum gain error 2 , 3 1% fs maximum 1% fs maximum digital input = v inh supply rejection 4 ?gain/?v dd 0.001%/% maximum 0.001%/% maximum digital inputs = v inh , v dd = 14 v to 17 v output leakage current i out 1 5 na maximum 200 na maximum digital inputs = v inl , v ref = 10 v i out 2 5 na maximum 200 na maximum digital inputs = v inh , v ref = 10 v dynamic accuracy output current settling time 600 ns maximum 4 800 ns 5 to 0.05% fsr; r load = 100 , digital inputs = v inh to v inl or v inl to v inh feedthrough error 0.05% fsr maximum 5 0.1% fsr maximum 5 digital inputs = v inl , v ref = 10 v, 100 khz sine wave propagation delay 100 ns typical 100 ns typical glitch impulse 100 nv-s typical 100 nv-s typical reference input input resistance (vref) 5 k min, 20 k maximum 5 k min, 20 k maximum 6 11 k nominal analog outputs output capacitance c iout1 50 pf maximum 5 100 pf maximum 5 digital inputs = v inh c iout2 20 pf maximum 5 35 pf maximum 5 c iout1 30 pf maximum 5 35 pf maximum 5 c iout2 50 pf maximum 5 100 pf maximum 5 digital inputs = v inl digital inputs input high voltage (v inh ) 2.4 v minimum 2.4 v minimum input low voltage (v inl ) 0.8 v maximum 0.8 v maximum input leakage current (i in ) 1 a maximum 1 a maximum v in = 0 v and v dd input capacitance (c in ) 8 pf maximum 5 8 pf maximum 5 power requirements v dd 15 v 10% 15 v 10% rated accuracy v dd ranges 5 5 v to 16 v 5 v to 16 v functionality with degraded performance i dd 2 ma maximum 2 ma maximum digital inputs = v inl or v inh d 25 a maximum 50 a maximum digital inputs over v in 1 fsr = full-scale range. 2 full scale (fs) = v ref . 3 maximum gain change from t a = 25c to t min or t max is 0.1% fsr. 4 ac parameter, sample tested to ensure specification compliance. 5 guaranteed, not tested. 6 absolute temperature coefficie nt is approximately ?300 ppm/c.
ad7533 rev. c | page 4 of 12 absolute maximum ratings t a = 25 c unless otherwise noted. table 2. parameter rating v dd to gnd ?0.3 v, +17 v r fb to gnd 25 v v ref to gnd 25 v digital input voltage range ?0.3 v to v dd + 0.3 v i out 1, i out 2 to gnd ?0.3 v to v dd power dissipation (any package) to 75c 450 mw derates above 75c by 6 mw/c operating temperature range plastic (jn, jp, kn, kp, ln versions) ?40c to +85c hermetic (aq, bq, cq versions) ?40c to +85c hermetic (sq, te, uq versions) ?55c to +125c storage temperature range ?65c to +150c lead temperature (soldering, 10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7533 rev. c | page 5 of 12 terminology relative accuracy relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for ideal zero and full scale and is expressed in % of full-scale range or (sub) multiples of 1 lsb. resolution value of the lsb. for example, a unipolar converter with n bits has a resolution of (2 Cn ) (v ref ). a bipolar converter of n bits has a resolution of [2 C(nC1) ] (v ref ). resolution in no way implies linearity. settling time time required for the output function of the dac to settle to within ? lsb for a given digital input stimulus, that is, 0 to full scale. gain error gain error is a measure of the output error between an ideal dac and the actual device output. it is measured with all 1s in the dac after offset error is adjusted out and is expressed in lsbs. gain error is adjustable to zero with an external potentiometer. feedthrough error error caused by capacitive coupling from v ref to output with all switches off. output capacitance capacity from i out 1 and i out 2 terminals to ground. output leakage current current that appears on i out 1 terminal with all digital inputs low or on i out 2 terminal when all inputs are high.
ad7533 rev. c | page 6 of 12 pin configurations and function descriptions i out 1 1 i out 2 2 gnd 3 bit 1 (msb) 4 r fb 16 v ref 15 v dd 14 bit 10 (lsb) 13 bit 2 5 bit 3 6 bit 4 7 bit 9 12 bit 8 11 bit 7 10 bit 5 8 bit 6 9 ad7533 top view (not to scale) 01134-002 figure 2. 16-lead pdip pin configuration 01134-003 i out 1 1 i out 2 2 gnd 3 bit 1 (msb) 4 r fb 16 v ref 15 v dd 14 bit 10 (lsb) 13 bit 2 5 bit 9 12 bit 3 6 bit 8 11 bit 4 7 bit 7 10 bit 5 8 bit 6 9 ad7533 top view (not to scale) figure 3. 16-lead soic pin configuration i out 1 1 i out 2 2 gnd 3 bit 1 (msb) 4 r fb 16 v ref 15 v dd 14 bit 10 (lsb) 13 bit 2 5 bit 9 12 bit 3 6 bit 8 11 bit 4 7 bit 7 10 bit 5 8 bit 6 9 ad7533 top view (not to scale) 01134-004 figure 4. 16-lead cerdip pin configuration 4 gnd 5 bit 1 (msb) 6 nc 7 bit 2 8 bit 3 18 v dd 17 bit 10 (lsb) 16 nc 15 bit 9 14 bit 8 19 v ref 20 r fb 1 nc 2 i out 1 3 i out 2 13 bit 7 12 bit 6 11 nc 10 bit 5 9 bit 4 ad7533 top view (not to scale) nc = no connect 01134-005 figure 5. 20-terminal lcc pin configuration 01134-006 12019 23 4 5 6 7 8 18 17 16 15 14 9 10 11 12 13 nc = no connect gnd bit 1 (msb) nc bit 2 bit 3 v dd bit 10 (lsb) nc bit 9 bit 8 i out 2 i out 1 nc r fb v ref bit 4 bit 5 nc bit 6 bit 7 pin 1 indentfier ad7533 top view (not to scale) figure 6. 20-lead plcc pin configuration table 3. pin function descriptions pin umber 16-lead pdip, soic, cerdip 20-lead lcc, plcc mnemonic description 1 2 i out 1 dac current output. 2 3 i out 2 dac analog ground. this pin should normally be tied to the analog ground of the system. 3 4 gnd ground. 4 to 13 5, 7 to 10, 12 to 15, 17 bit 1 to bit 10 msb to lsb. 14 18 v dd positive power supply input. these parts can be operated from a supply of 5 v to 16 v. 15 19 v ref dac reference voltage input terminal. 16 20 r fb dac feedback resistor pin. establish voltage output for the dac by connecting r fb to external amplifier output. na 1, 6, 11, 16 nc no connect.
ad7533 rev. c | page 7 of 12 circuit description general circuit information the ad7533 is a 10-bit multiplying dac that consists of a highly stable thin-film r-2r ladder and ten cmos current switches on a monolithic chip. most applications require the addition of only an output operational amplifier and a voltage or current reference. the simplified d/a circuit is shown in figure 7 . an inverted r- 2r ladder structure is used, that is, the binarily weighted currents are switched between the i out 1 and i out 2 bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. 20k ? s1 s2 s3 sn i out 2 v ref i out 1 r fb 20k ? 20k ? 20k ? 10k ? bit 1 (msb) bit 10 (lsb) digital inputs (dtl/ttl/cmos compatible) bit 2 bit 3 10k ? 10k ? 10k ? 20k ? 01134-001 figure 7. functional diagram one of the cmos current switches is shown in figure 8 . the geometries of device 1, device 2, and device 3 are optimized to make the digital control inputs dtl/ttl/cmos compatible over the full military temperature range. the input stage drives two inverters (device 4, device 5, device 6, and device 7), which in turn drive the two output n channels. the on resistances of the switches are binarily sealed so that the voltage drop across each switch is the same. for example, switch 1 in figure 8 is designed for an on resistance of 20 , switch 2 for 40 , and so on. for a 10 v reference input, the current through switch 1 is 0.5 ma, the current through switch 2 is 0.25 ma, and so on, thus maintaining a constant 10 mv drop across each switch. it is essential that each switch voltage drop be equal if the binarily weighted current division property of the ladder is to be maintained. dtl/ttl/ cmos input v + 13 2 to ladder 5 4 250 ? 7 6 89 i out 1 i out 2 01134-007 figure 8. cmos switch equivalent circuit analysis the equivalent circuits for all digital inputs high and digital inputs low are shown in figure 9 and figure 10 . in figure 9 with all digital inputs low, the reference current is switched to i out 2. the current source i leakage is composed of surface and junction leakages to the substrate, while the i/1024 current source represents a constant 1-bit current drain through the termination resistor on the r-2r ladder. the on capacitance of the output n channel switch is 100 pf, as shown on the i out 2 terminal. the off switch capacitance is 35 pf, as shown on the i out 1 terminal. analysis of the circuit for all digital inputs high, as shown in figure 10 , is similar to figure 9 ; however, the on switches are now on ter mina l i out 1. therefore, there is the 100 pf at that terminal. i out 2 i out 1 v ref i ref r fb i leakage r 01134-008 r r 10k ? 100pf i leakage 35pf i/1024 figure 9. equivalent circuitall digital inputs low i out 2 i out 1 v ref i ref r fb i leakage r 01134-009 r 100pf i leakage 35pf i/1024 r 10k ? figure 10. equivalent circuitall digital inputs high
ad7533 rev. c | page 8 of 12 operation unipolar binary code table 4. unipolar binary operation (2-quadrant multiplication) digital input analog output msb lsb (v out as shown in figure 11 ) 1 1 1 1 1 1 1 1 1 1 ? ? ? ? ? ? ? 1024 1023 ref v 1 0 0 0 0 0 0 0 0 1 ? ? ? ? ? ? ? 1024 513 ref v 1 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? = ? ? ? ? ? ? ? 2 1024 512 ref ref v v 0 1 1 1 1 1 1 1 1 1 ? ? ? ? ? ? ? 1024 511 ref v 0 0 0 0 0 0 0 0 0 1 ? ? ? ? ? ? ? 1024 1 ref v 0 0 0 0 0 0 0 0 0 0 0 1024 0 = ? ? ? ? ? ? ? ref v nominal lsb magnitude for the circuit of figure 11 is given by ? ? ? ? ? ? = ref vlsb 3 14 1 16 2 15 4 13 ad7533 unipolar digital input msb v dd v ref i out 1 v out i out 2 r fb c1 gnd bipolar analog input 10v r1 1k ? r2 330 ? lsb notes 1. r1 and r2 used only if gain adjustment is required. 2. c1 phase compensation (5pf to 15pf) may be required when using high speed amplifier. 01134-010 figure 11. unipolar binary operation (2-quadrant multiplication) bipolar (offset binary) code table 5. unipolar binary operation (4-quadrant multiplication) digital input analog output msb lsb (v out as shown in figure 12 ) 1 1 1 1 1 1 1 1 1 1 ? ? ? ? ? ? + 512 511 ref v 1 0 0 0 0 0 0 0 0 1 ? ? ? ? ? ? + 512 1 ref v 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 ? ? ? ? ? ? ? 512 1 ref v 0 0 0 0 0 0 0 0 0 1 ? ? ? ? ? ? ? 512 511 ref v 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? 512 512 ref v nominal lsb magnitude for the circuit of figure 12 is given by ? ? ? ? ? ? = ref vlsb 3 14 1 16 2 15 4 13 ad7533 bipolar digital input msb v dd v ref i out 1 v out i out 2 c1 gnd a1 a2 10v bipolar analog input r1 1k? r2 330 ? r3 10k ? r6 5k? r4 20k ? lsb notes 1. r3, r4, and r5 selected for matching and tracking. 2. r1 and r2 used only if gain adjustment is required. 3. c1 phase compensation (5pf to 15pf) may be required when using high speed amplifiers. 01134-011 r5 20k ? figure 12. bipolar operation (4-quadrant multiplication)
ad7533 rev. c | page 9 of 12 applications 3 14 1 16 2 15 4 13 ad7533 op97 op97 magnitude bits sign bit digital input msb v dd v ref i out 1 v out i out 2 r fb gnd bipolar analog input 10v 10k? 10k? 5k? 1/2 ad7512dijn lsb 01134-012 figure 13. 10-bit and sign multiplying dac 3 14 1 16 2 15 4 13 ad7533 op97 op97 digital frequency control word msb +15v v dd nc v ref i out 1 6.8v (2) square wave triangular wave i out 2 c t gnd calibrate 10v 1k ? 4.7k ? lsb 01134-013 10k ? 1% 10k ? 1% f = n ( ) r t = 10k ? 0 < n (1 2 10 ) 1 8 r t c t figure 14. programmable function generator 3 16 2 1 14 15 4 13 ad7533 digital input ?d? bit 1 bit 10 msb v ref i out 2 v out v in i out 1 r fb gnd +15 v lsb 01134-014 v out = d= + where: ?v in d 0 < d bit 1 2 1 bit 2 2 2 +? bit 10 2 10 1023 1024 figure 15. divider (digitally controlled gain) 3 14 1 16 2 15 4 13 ad7533 digital input ?d? msb +15v v ref ?v refd v ou t r fb gnd r1 r2 lsb 0 113 4 - 015 bit 1 bit 10 v out = v ref = ? d= + where: r 2 r 1 + r 2 0 < d bit 1 2 1 bit 2 2 2 +? bit 10 2 10 1023 1024 r 1 d r 1 + r 2 i out 1 i out 2 figure 16. modified scale factor and offset 3 14 1 16 2 15 4 13 ad7533 ad790 comparator digital input (test limit) msb +15v test input (0 to ? v ref ) i out 1 fail/pass test i out 2 gnd v ref lsb 01134-016 figure 17. digitally programmable limit detector .
ad7533 rev. c | page 10 of 12 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001-ab 073106-b 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 16 1 8 9 0.100 (2.54) bsc 0.800 (20.32) 0.790 (20.07) 0.780 (19.81) 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 18. 16-lead plastic dual in-line package [pdip] (n-16) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013- aa 112906-b 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc figure 19. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches)
ad7533 rev. c | page 11 of 12 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.840 (21.34) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 0 .200 (5.08) max 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) min 0.098 (2.49) max 0.100 (2.54) bsc pin 1 1 8 9 16 seating plane 0.150 (3.81) min 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) figure 20. 16-lead ceramic dual in-line package [cerdip] (q-16) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 1 20 4 9 8 13 19 14 3 18 bottom view 0.028 (0.71) 0.022 (0.56) 45 typ 0.015 (0.38) min 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) bsc 0.075 (1.91) ref 0.011 (0.28) 0.007 (0.18) r typ 0.095 (2.41) 0.075 (1.90) 0.100 (2.54) ref 0.200 (5.08) ref 0.150 (3.81) bsc 0.075 (1.91) ref 0.358 (9.09) 0.342 (8.69) sq 0.358 (9.09) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) 022106-a figure 21. 20-terminal cerami c leadless chip carrier [lcc] (e-20-1) dimensions shown in inches and (millimeters) compliant to jedec standards mo-047-aa controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.020 (0.50) r bottom view (pins up) 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.290 (7.37) 0.032 (0.81) 0.026 (0.66) 0.056 (1.42) 0.042 (1.07) 0.20 (0.51) min 0.120 (3.04) 0.090 (2.29) 3 4 19 18 8 9 14 13 top view (pins down) 0.395 (10.03) 0.385 (9.78) sq 0.356 (9.04) 0.350 (8.89) sq 0.048 (1.22 ) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.020 (0.51) r 0.050 (1.27) bsc 0.180 (4.57) 0.165 (4.19) 0.045 (1.14) 0.025 (0.64) r pin 1 identifier figure 22. 20-lead plastic leaded chip carrier [plcc] (p-20) dimensions shown in inches and (millimeters)
ad7533 rev. c | page 12 of 12 ordering guide model temperature range package description package option nonlinearity (% fsr max) ad7533achips die ad7533jn ?40c to +85c 16-lead plastic dual in-line package [pdip] n-16 0.2 ad7533jnz 1 ?40c to +85c 16-lead plastic dual in-line package [pdip] n-16 0.2 ad7533kn ?40c to +85c 16-lead plastic dual in-line package [pdip] n-16 0.1 ad7533knz 1 ?40c to +85c 16-lead plastic dual in-line package [pdip] n-16 0.1 ad7533ln ?40c to +85c 16-lead plastic dual in-line package [pdip] n-16 0.05 ad7533lnz 1 ?40c to +85c 16-lead plastic dual in-line package [pdip] n-16 0.05 ad7533jp ?40c to +85c 20-lead plastic leaded chip carrier [plcc] p-20 0.2 ad7533jp-reel ?40c to +85c 20-lead plastic leaded chip carrier [plcc] p-20 0.2 ad7533jpz 1 ?40c to +85c 20-lead plastic leaded chip carrier [plcc] p-20 0.2 ad7533jpz-reel 1 ?40c to +85c 20-lead plastic leaded chip carrier [plcc] p-20 0.2 ad7533kp ?40c to +85c 20-lead plastic leaded chip carrier [plcc] p-20 0.1 ad7533kp-reel ?40c to +85c 20-lead plastic leaded chip carrier [plcc] p-20 0.1 ad7533kpz 1 ?40c to +85c 20-lead plastic leaded chip carrier [plcc] p-20 0.1 ad7533kpz-reel 1 ?40c to +85c 20-lead plastic leaded chip carrier [plcc] p-20 0.1 ad7533kr ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 0.1 ad7533kr-reel ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 0.1 ad7533krz 1 ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 0.1 AD7533KRZ-REEL 1 ?40c to +85c 16-lead standard small outline package [soic_w] rw-16 0.1 ad7533aq ?40c to +85c 16-lead ceramic dual in-line package [cerdip] q-16 0.2 ad7533bq ?40c to +85c 16-lead ceramic dual in-line package [cerdip] q-16 0.1 ad7533cq ?40c to +85c 16-lead ceramic dual in-line package [cerdip] q-16 0.05 ad7533sq ?55c to +125c 16-lead ceramic dual in-line package [cerdip] q-16 0.2 ad7533uq ?55c to +125c 16-lead ceramic dual in-line package [cerdip] q-16 0.05 ad7533uq/883b ?55c to +125c 16-lead ceramic dual in-line package [cerdip] q-16 0.05 ad7533te/883b ?55c to +125c 20-terminal ceramic leadless chip carrier [lcc] e-20-1 0.1 t 1 z = rohs compliant part. ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c01134-0-3/07(c) ttt

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